The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a pattern in a semiconductor device.
As semiconductor devices have become highly integrated, pattern micronization is generally required. Yet, it is difficult to embody a device having a micro pattern of 40 nm or less due to resolution limitations of currently developed photo-exposure apparatuses.
In order to overcome such limitations, a double patterning technology and a spacer patterning technology have been recently introduced. The double patterning technology includes forming a micro pattern by performing a photolithography process two times. The spacer patterning technology includes patterning using spacers.
In particular, the spacer patterning technology is appraised to be more improved than the double patterning technology because the spacer patterning technology overcame the lack of overlay margin which was a technological weak point of the double patterning technology.
The spacer patterning technology may largely be divided into a positive spacer patterning technology and a negative spacer patterning technology. The positive spacer patterning technology includes using spacers as a direct mask in a pattern formation process. The negative spacer patterning technology includes using space between spacers.
For instance, the positive spacer patterning technology includes forming an etch stop layer and a sacrificial layer over an etch-target layer. A photoresist pattern is formed over the sacrificial layer, the photoresist pattern having a pitch greater than a photo-exposure pitch limit. The sacrificial layer is etched using the photoresist pattern to form a sacrificial pattern. Spacers are formed on both sides of the sacrificial pattern.
The sacrificial pattern is then removed. The etch stop layer and the etch-target layer are etched using the remaining spacers. Thus, an etch-target pattern having a value of a photo-exposure pitch limit or less may be formed.
Meanwhile, the negative spacer patterning technology includes forming an etch stop layer and a sacrificial layer over an etch-target layer. A photoresist pattern is formed over the sacrificial layer, the photoresist pattern having a value of a photo-exposure pitch limit or greater. The sacrificial layer is etched using the photoresist pattern to form a sacrificial pattern. Spacers are formed on both sides of the sacrificial pattern.
A capping layer is formed over the resultant structure including the sacrificial pattern and the spacers. A planarization process is performed on the structure until the spacers are exposed. Thus, a capping pattern filled between the spacers is formed. The spacers are then removed. The etch stop layer and the etch-target layer are etched using the remaining sacrificial pattern and the capping pattern. Thus, an etch-target pattern having a value of a photo-exposure pitch limit or less may be formed.
The positive spacer patterning technology or the negative spacer patterning technology is selectively used when forming a pattern in a semiconductor device. However, the semiconductor device may not include uniformly sized patterns. It is highly likely that the semiconductor device includes both a region where patterns having a small width are formed, e.g., a cell region, and another region where patterns having a relatively large width are formed, e.g., a peripheral region.
Thus, selectively using one of the positive spacer patterning technology and the negative spacer patterning technology when forming a pattern in a semiconductor device may bring about disadvantages as well as merits.
For instance, when forming gate patterns in a cell region and a peripheral region using the positive spacer patterning technology, the gate patterns in the cell region are formed densely in an even number. Thus, the gate patterns may be formed with ease using an even number of spacers formed on both sides of sacrificial patterns.
However, gate patterns in the peripheral region have a relatively large width than those in the cell region. Thus, it is difficult to form the gate patterns solely using spacers. An additional mask process is generally required, and thus, an overlay limitation, similar to that often occurring in the double patterning technology, may be generated.
Meanwhile, when forming gate patterns in a cell region and a peripheral region using the negative spacer patterning technology, it may be easier to form gate patterns in the peripheral region having a relatively large width than those in the cell region because the gate patterns are formed using spaces between spacers. However, one of the gate patterns has to be removed because an odd number of gate patterns are formed in the cell region, causing difficulty in the process.